这是最近完成的关于HDB3编码的Verilog代码，经仿真，验证了结果正确，欢迎大家指正或完善。
module code_hdb3(clk,reset,data,code_out);
input clk,reset,data;
output[1:0] code_out;
reg[1:0] code_out;
//变量声明
reg flag_v,flag_b;
reg count,count_1;
reg[1:0] count_0,count_reg,Idle;
reg[4:0] data_reg;
reg[7:0] count_10;
//找出移位后的B码插入的位置
always @(posedge clk)
begin
if(!reset) begin
flag_v<=0;
count_0<=0;
count_1<=0;
end
else begin
count_1<=count_1^data;
if(data==0) begin
count_0<=count_0+1;
if(count_0==2'b11)
begin
flag_v<=1;
count_1<=0;
end
else
flag_v<=0;
end
else begin
count_0<=0;
flag_v<=0;
end
end
end
always@(posedge clk)
begin
if(!reset) begin
flag_b<=0;
count_10<=0;
end
else begin
if(count_1==0) begin
count_10<=count_10+1;
begin
if(flag_v==1&&count_10>3)
begin
if(count_1==0)
flag_b<=1;
else
flag_b<=0;
end
end
end
else begin
count_10<=0;
flag_b<=0;
end
end
end
//把原数据放到寄存器中
always@(posedge clk)
begin
if(!reset)
data_reg<=5'b11000;
else begin
data_reg[0]<=data_reg[1];
data_reg[1]<=data_reg[2];
data_reg[2]<=data_reg[3];
data_reg[3]<=data_reg[4];
data_reg[4]<=data;
end
end
always@(posedge clk)
begin
if(!reset)
count_reg<=0;
else begin
if(data_reg[0]==0)
count_reg<=count_reg+1;
else
count_reg<=0;
end
end
//编码输出
always@(posedge clk)
begin
if(!reset) begin
code_out<=2'b00;
count<=0;
Idle<=2'b01;
end
else begin
count<=count+data_reg[0]+flag_b;
if(data_reg[0]==1||flag_b==1)
begin
if(count) begin
code_out<=2'b01;
Idle<=2'b01;
end
else begin
code_out<=2'b11;
Idle<=2'b11;
end
end
else begin
if(data_reg[0]==0&&count_reg==2'b11)
code_out<=Idle;
else
code_out<=2'b00;
end
end
end
endmodule
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