module decode(clk,reset,data,out);
input clk,reset;
input[1:0] data;
output out;
reg out;
//变量声明；
reg flag;
reg[1:0] reg_m,reg_m1;
reg[7:0] reg_s;
//破坏符号V标志查找；
always@(posedge clk)
begin
if(!reset) begin
flag<=0;
reg_m<=2'b01;
end
else begin
if(data!=reg_m&&data!=2'b00)
begin
flag<=0;
reg_m<=data;
end
else begin
if(data==reg_m)
flag<=1;
else
flag<=0;
end
end
end
//将消息代码送入寄存器中；
always@(posedge clk)
begin
if(!reset)
reg_s<=10'b00;
else begin
reg_s[1:0]<=reg_s[3:2];
reg_s[3:2]<=reg_s[5:4];
reg_s[5:4]<=reg_s[7:6];
reg_s[7:6]<=data;
end
end
//译码输出；
always@(posedge clk)
begin
if(!reset)
reg_m1<=2'b01;
else begin
if(reg_s[1:0]!=reg_m1&®_s[1:0]!=2'b00)
reg_m1<=reg_s[1:0];
end
end
always@(posedge clk)
begin
if(!reset) out<=0;
else begin
if(flag==1||reg_s[1:0]==reg_m1||reg_s[1:0]==2'b0)
out<=0;
else
out<=1;
end
end
endmodule
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